The present invention relates to a semiconductor memory having an overlaid bus structure and a control circuit for the same.
Recent demands for reduction in the number of parts of apparatuses associated with a trend toward portable apparatuses, reduction in power consumption, and higher speed and expanded bit widths for improved data transfer efficiency have resulted in an increased need for the so-called memories combined with logic wherein memories of various capacities and configurations are combined with logic systems performing various kinds of data processing into a single IC chip.
In most cases, a bus for exchanging data between a memory portion and a logic portion has a constant width, e.g., 64 or 128 bits. In order to satisfy various requirements of such systems mixed with a logic portion or the like, it is desirable that a memory portion is configured to have a data bus width which remains unchanged irrespective of changes in an address configuration or memory capacity.
In order to satisfy such a need, memory systems having an overlaid bus structure have been proposed.
FIG. 16 shows a circuit configuration of memory cell arrays of a memory system having an overlaid bus structure and a peripheral portion of the same. FIG. 16 focuses on three memory cell arrays among a plurality of memory cell arrays which constitute a memory system. The memory system shown in FIG. 16 employs a shared sense amplifier system in which a sense amplifier is shared by memory cells in adjoining memory cell arrays.
The memory system is formed by memory cell arrays MCAixe2x88x921, MCAi, and MCAi+1, data line pairs DATA0 through DATA255 shared by the memory cell arrays, sense amplifiers S/A and S/A1 through S/A4, column switches CSW, CSW1, and CSW2, and a decoder circuit DEC. Each memory cell array has 256 lines and 1024 columns and has 1024 bit line pairs and 256 word lines which are not shown. FIG. 16 shows only bit lines pairs BL and BL1 through BL4. The sense amplifiers S/A and S/A1 through S/A4 are shared by adjoining memory cell arrays. For example, the sense amplifier S/A1 is shared by the memory cell arrays MCAi and MCAixe2x88x921, and the sense amplifier S/A2 is shared by the memory cell arrays MCAi and MCAi+1.
BL1 through BL4 of the memory cell array MCAi are connected to sense amplifiers S/A1 through S/A4, respectively. The sense amplifiers S/A1 and S/A3 are connected to the data line pair DATA0 through the columns switch CSW1, and the sense amplifiers S/A2 and S/A4 are connected to the data line pair DATA0 through the column switch CSW2. Therefore, the four sense amplifiers S/A1 through S/A4 of the memory cell array MCA1 can be connected to the pair of data lines DATA0. That is, each memory cell array has a common data line pair for every four bit lines. Although not shown, since a memory cell array has 1024 bit line pairs, there are 1024/4=256 pairs of data lines DATA. The operation of this memory system will be described below with reference to an example wherein data on the memory cell array MCAi are read on the data line pairs DATA0 through DATA255.
According to a row address, the decoder circuit DEC selects one word line of the desired memory cell array MCAi. The data on the bit line pairs BL1 through BL4 designated by the selected word line are transmitted to the sense amplifiers S/A1 through S/A4 to activate MCAi. Further, when the sense operation of the sense amplifiers S/A1 through S/A4 is complete, the decoder circuit DEC controls turning on/off of the column switches CSW1 and CSW2 according to a column address to transmit the data sensed and held by one of the sense amplifiers S/A1 through S/A4 to the data line pair DATA0. Thus, the data in the memory cell selected according to the column address on the word line selected according to the row address are transmitted to the data line pair DATA0. Since data are similarly transmitted to the data line pairs DATA1 through DATA255, data are transmitted to 256 pairs of data lines in total.
FIG. 17 shows a configuration of a memory system with a data bus having a width of 128 I/O as an example of a memory system utilizing the above-described overlaid structure.
The memory system is formed by two blocks 1701 and 1702 which are each formed by sixteen memory cell arrays MCA0 through MCA15 and MCA16 through MCA31, respectively. Each of the memory cell arrays has 256 rows and 1024 columns, which means that the total capacity of the memory system is 8 megabit.
There are groups of data lines 1704 and 1705 each consisting of 256 data lines which can be connected to the memory cell arrays MCA0 through MCA15 and MCA16 through MCA31, respectively, in the direction of the bit lines of the memory cell arrays. The groups of data lines 1704 and 1705 are connected to column decoders 1706 and 1707, respectively. A decoder circuit 1703 is provided between the blocks 1701 and 1702 and is shared by those blocks to control the selection of word lines and column switches in each of the blocks simultaneously.
The decoder circuit 1703 selects arbitrary word lines of, for example, the memory cell arrays MCA5 and MCA21 according to a row address input thereto. The data on the selected word lines are transmitted to the sense amplifier to be sensed (memory cell arrays MCA5 and MCA21 are activated). Next, the decoder circuit 1703 selects the sense amplifier according to a column address input thereto to transmit the data to the groups of data lines 1704 and 1705. The groups of data lines 1704 and 1705 are connected to the column decoders 1706 and 1707, respectively. The column decoders 1706 and 1707 select 64 data lines from among the respective 256 data lines and connect them to data buses 1708 and 1709, respectively.
As described above, there are upper and lower data buses of 64 I/O each which provide an overall bus width of 128 I/O.
The capacity of a memory system having such a structure can be increased or decreased by increasing or decreasing the number of memory cell arrays MCA. However, this will not increase or decrease the number of the data lines. It is therefore possible to always maintain a constant data bus width.
A description will now be made on a case wherein data are read from the memory cell arrays MCA13 and MCA29 after the data in the memory cell arrays MCA5 and MCA21 are read.
First, the data in the memory cell arrays MCA5 and MCA21 are read according to the procedure described above. Next, the decoder circuit resets and precharges the memory cell arrays MCA5 and MCA21 which have been in an activated state. Then, the decoder circuit 1703 selects arbitrary word lines of the memory cell arrays MCA13 and MCA29 according to a row address input thereto. The data on the selected word lines are transmitted to the sense amplifier to be sensed (memory cell arrays MCA13 and MCA29 are activated). Next, the decoder circuit 1703 selects the sense amplifier according to a column address input thereto to transmit the data to the groups of data lines 1704 and 1705. The data on the groups of data lines 1704 and 1705 are input to the column decoders 1706 and 1707, respectively. The column decoders 1706 and 1707 select 64 data lines from among the respective 256 data lines and connect them to data buses 1708 and 1709, respectively.
As described above, the memory cell arrays are activated and precharged according to the row addresses decoded by the decoder circuit 1703. Therefore, the operation of reading the data in the different memory cell arrays proceeds in a sequence such that the memory cell arrays MCA5 and MCA21 are activated; the data are read from the same; the memory cell arrays MCA5 and MCA21 are reset and precharged; the memory cell arrays MCA13 and MCA29 are activated; and then the data are read from the same. Thus, the operations of activating, resetting and precharging a memory cell are required each time it is read.
Further, in the above-described example, one each memory cell array is activated in the blocks 1701 and 1702 simultaneously. However, it is possible to activate a plurality of memory cell arrays simultaneously by adjusting the numbers of bits of addresses. input to a word line selection portion and a column switch selection portion (which are not shown) in the decoder circuit 1703. For example, if one of the bits of an input row address is used for controlling a column switch along with a column address instead of being used for selecting a word line, two memory cell arrays are activated in each of the blocks 1701 and 1702. In this case, the memory cell arrays MCA0, MCA8, MCA16, and MCA24 are activated simultaneously and, similarly, the memory cell arrays MCA5, MCA13, MCA21, and MCA29 are activated simultaneously.
Thus, when two memory cell arrays are simultaneously activated in each of the blocks 1701 and 1702, the operation of reading the data in the memory cell arrays MCA13 and MCA29 after reading the data in the memory cell arrays MCA5 and MCA21 as described above proceeds in a sequence such that the memory cell arrays MCA5, MCA13, MCA21, and MCA29 are activated; data are read from the memory cell arrays MCA5 and MCA13 are read; and then data are read from the memory cell arrays MCA13 and MCA29. Thus, the resetting and precharging of the memory cells can be omitted.
Even in such a case, however, there are predetermined combinations of memory cell arrays that can be activated simultaneously, and the activation, resetting, and precharging are required for an operation of reading data from memory cell arrays which are not activated simultaneously (e.g., MCA5, MCA21 and MCA3 and MCA19).
As described above, in a conventional memory system of the overlaid type, memory cell arrays must be activated, reset, and precharged when data are read therefrom, which has placed a limit on efforts for increasing the speed of data reading operations.
It is an object of the present invention to provide an overlaid type memory system in which any reduction in the speed of reading from different memory cell arrays associated with activation, resetting, and precharging of the same is avoided by activating each of the memory cell arrays independently of other memory cell arrays and by maintaining each of the memory cell arrays in an activated state.
The object of the present invention is achieved by the configurations described below.
According to a first aspect of the present invention, there is provided a one chip semiconductor system comprising:
a plurality of memory cell arrays which are independently controllable; and
a bus commonly provided for each memory cell array, the bus including;
an address bus and a control signal bus which are logically dividable;
an address signal transmitted through the address bus; and
a control signal transmitted through the control signal bus, wherein the control signal bus is synchronized with the address signal;
wherein a predetermined memory cell array designated by the address signal is operated by the control signal based on a timing at which the control signal reaches the predetermined memory cell array.
According to a second aspect of the present invention, there is provided a one chip semiconductor system comprising:
a plurality of memory cell arrays which are independently controllable; and
a bus commonly provided for each memory cell array, the bus logically divided into a data bus, an address bus and a control signal bus, wherein the control signal bus includes;
a plurality of control signal lines;
a control signal pulse transmitted through the plurality of control signal lines; and
an address signal pulse transmitted through the address bus, wherein the control signal pulse is synchronized with the address signal pulse;
wherein a predetermined memory cell array designated by the address signal pulse is operated by the control signal pulse based on a timing at which the control signal pulse reaches the predetermined memory cell array.
According to a third aspect of the present invention, there is provided a one chip semiconductor system, comprising:
a plurality of memory cell arrays which are independently controllable, each memory cell array having a particular address;
a bus commonly provided for each memory cell array, the bus including;
an address bus and a control signal bus which are logically dividable;
an address signal corresponding to the particular address transmitted through the address bus; and
a control signal transmitted through the control signal bus, wherein the control signal is synchronized with the address signal; and
a plurality of memory cell array control portions each provided for an associated memory cell array of the plurality of the memory cell arrays, each memory cell array control portion including a decoder for discriminating the address signal, the each memory cell array control portion activating the memory cell array having the particular address consistent with the address signal;
wherein a predetermined memory cell designated by the address signal is operated by the control signal based on a timing at which the control signal reaches the predetermined memory cell array.
Additional object and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The object and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.